The present invention is related to methods for producing the printed pattern of interconnection lines of wafers such as semiconductor wafers used for photovoltaic (solar) cells and the like.
There exist today a very wide variety of devices whose starting point is a wafer substrate. For example, integrated circuit devices are often formed on thin, circular silicon wafers on which a pattern of various materials have been formed. A large number of other discrete and integrated devices are similarly produced by forming patterns of materials on wafer substrates. Similarly, certain forms of the ubiquitous disk drive begins with a platter on which a pattern of features are formed (such as texture bumps to reduce stiction and the like).
One type of device formed from a patterned substrate is a photovoltaic cell. A subset of these devices are those which generate a current using sunlight, or solar cells, which are of particular interest today as a source of environmentally conscious energy generation. In the present disclosure we focus on the manufacturing process and design of such solar cells, although it will be appreciated that this is but one example of the types of devices, wafer processes, and wafer designs to which the present disclosure is addressed.
One example of a modern solar cell is formed of a body, typically silicon, in which a p-n junction diode is formed (e.g., by diffusion of an n+ dopant into a surface of the p-type body). In operation, a photon absorbed by the body (e.g., from sunlight) “excites” an atom of the body material causing an increase in the energy of an electron of that atom. This increase in energy moves the electron into the conduction band, where it is free to move around within the semiconductor. The vacancy left by the now-mobile electron is called a hole. The negative charge of the electron causes it to flow in one direction within the body (e.g., toward the n-type region), and the positive charge of the hole causes it to flow in the opposite direction (e.g., toward the p-type region). An array of grid lines (parallel lines and/or intersecting lines) are formed on a surface of the body to permit the collection of the mobile electrons or holes, thereby permitting extraction of a direct current. In some cases, contact pads are provided as terminations for the lines in order to provide a convenient mechanism for connection of the solar cell to external circuitry.
While there are a number of popular solar cell designs on the market today, they generally have in common the grid array on one surface of the body. (As used herein, the term “grid array” shall denote parallel line, intersecting line, and both parallel and intersecting line embodiments.) The surface of the body can either be the “frontside” or “backside”, where the frontside is that surface exposed to sun and the backside is the side opposite the frontside. For efficient operation of all solar cell designs it is desired to provide a relatively large area within which photons may be absorbed. The electrons and holes generated by the photons cannot travel far without recombining (producing no useful current). Therefore, the grid array must be in electrical contact with (i.e., cover) a significant portion of the body surface. In addition, the lines must have sufficiently low resistivity and a sufficient cross-sectional area to carry the generated current. Too high the cross sectional resistance and the current is attenuated.
According to one solar cell design referred to as a backside contact design, emitter regions are formed in the bulk body proximate the backside of the body. Base and emitter contacts are then formed on the backside, with the emitter contacts in electrical contact with the emitter regions in the body. In a variation of this design, referred to as the metallization wrap-through back contact cell design, the emitter remains near the frontside of the body, but part of the front metallization grid is moved from the front to the rear surface, and the remaining front surface grid is connected to the interconnection pads on the rear surface by extending it though a number of vias formed in the body. In either backside embodiment, however, there is a desire to provide as many base-emitter pair as possible in order to obtain the current from the cell.
Typically, in any process which covers a wafer in a metal film or deposits a patterned layer over the wafer, deposition or patterning up to the edge of a wafer is problematic due to wafer size variations, wafer quality at its edge, and particularly for patterning, screen printing tolerances, screen stretch, etc. Most processes impose a limit on how close to the wafer edge a process may pattern the wafer surface. Width of such a region, called an edge exclusion zone, varies based on process, material being deposited, wafer material, etc., but a typical design limitation is an edge exclusion zone on the order of 1 mm wide.
One key reason for the edge exclusion zone is that wafers vary in size, edge quality, etc. from wafer to wafer. It is possible to increase the consistency of the wafers and the quality of the wafer edges from wafer to wafer, but doing so increases wafer cost significantly. The solar cell industry, and indeed many wafer-based industries, are very sensitive to cost increases. Therefore, there is a need to provide a reduction in the edge exclusion zone (i.e., provide increased usable wafer area) without materially increasing cost.
Features patterned onto the surface of a body of the type discussed above are often produced by a screening method. According to such methods, there is a minimum feature size limitation imposed by the limits of the screening process. Furthermore, the surface area of the body on which features may be printed is limited by the edge exclusion zone design rule. Therefore, to date there has been a limit on the total number of base-emitter feature pairs that may be present on a solar cell, which works against the desire to maximize the number of such feature pairs in order to maximize the output efficiency of the solar cell.
In fact, in most wafer-based structures, there is a desire to utilize as much of the wafer surface as possible. The edge exclusion zone rule typically is imposed on any such wafer-based structure. Therefore, the desire to find more useable surface area for example in the edge exclusion zone has applicability outside the field of solar cells.